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| www..com Specifications - June 2001 TCC110 1200 baud FSK (Frequency Shift Keying) demodulator with sensitivity -38dBm (in 600) conforms to Bell 202 and CCITT V.23 standards Receive sensitivity of -32dBm (in 600) for CAS ( CPE Alerting Signal ) Progress Tone Energy (PTE) detector with sensitivity of -27dBm Ring or Line Reversal detector Ring Frequency measurement Line voltage measurement DTMF generator with gain controller for all 16 characters On-hook and off-hook applications according to Bellcore TR-NWT-000030 and SR-TSV-002476 specifications TCC110 CIDCW receiver Caller-ID on Call Waiting (CIDCW) Receiver June 2001 Specifications FEATURES Compatible with ETSI standards ETS 300 659-1 and ETS 300 659-2 3V ~ 5V operation On-chip 3.579545MHz crystal oscillator Power-down mode 24-pin SOP package 0.5um CMOS triple metal process APPLICATIONS Bellcore CID and CIDCW systems CID and CIDCW feature phones and adjunct boxes Computer Telephony Integrated systems Voice-Mail Equipment D /A C o n ve rte r DTMFO DTMF G e ne ra to r C rysta l O scilla to r X IN XOUT VREF1 VREF IN S B a n dP a ss F ilte r G a in C o ntro lle r F S K R e ce iver ADC IN P IN N OUT IN D ADC B a n dP a ss F ilte r C AS D e te cto r P ro g re ss T o n e E n e rg y D e te cto r F re q u e n cy C o un te r D C vo ltag e m ea su rem e n t M od e C o ntro l & S e rial In te rfa ce SDT SCK IN T R in g D e te cto r VCCA VCCD VCCD P o w e r S u p ply C ircuit L in e R e ve rsa l / R in g D e te cto r V S SA V S SA V S SD V S SD L R IN T E ST TESTout R ES E T GENERAL DESCRIPTION The TCC110 is a low power CMOS device used for receiving physical layer signals like Bellcore's CPE Alerting Signal (CAS) and similar evolving systems. This device also meets the requirements of emerging Calller ID on Call Waiting (CIDCW) services. In addition, two different signal inputs are available to support Tip/Ring and Hybrid connectivity. The device also includes a 1200 baud Bell 202/V.23 compatible FSK data demodulator, a ring or line reversal detector, a Progress Tone Energy detector, a DTMF generator and a DC line voltage level measurement unit. The status of the TCC110, the received FSK data, the ring frequency and other received information can be read and control options can be written via the serial interface. An on-chip 3.579545MHz oscillator is available. In power-down mode only the ring or line reversal detector can be active. device is available in a 24-pin SOP package. www.telechips.com Page 1 / 34 Tel: 82-2-3443-6792 The operating voltage is 3V ~ 5V and the TCC110 www..com Specifications - June 2001 CIDCW receiver 1. PIN DESCRIPTIONS VSSD L R in TEST X IN XO UT VSSD VSSA VREF IN S IN P IN N OUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCD SCK TESTO UT SDT IN T RESET VCCD VCCA DTM FO VSSA VR EF1 IN D TCC110 TCC110 TCC110 Table 1: Pin descriptions Number Pin name 1 VSSD 2 Lrin 3 TEST 4 XIN 5 XOUT 6 VSSD 7 VSSA 8 VREF 9 INS 10 INP 11 INN 12 OUT 13 14 15 16 17 18 19 20 21 22 23 24 IND VREF1 VSSA DTMFO VCCA VCCD RESET INT SDT TESTOUT SCK VCCD Function Supply Schmitt Input Input Input Output Supply Supply Analog output Analog input Analog input Analog input Analog output Analog input Analog output Supply Analog output Supply Supply Input Open drain output Open drain input/output Output Input Supply Pin description Negative supply voltage ( ground ) Input for line reversal or ring detection Test pin, must be connected to ground 3.579545 MHz crystal input 3.579545 MHz crystal output Negative supply voltage (ground ) Negative supply voltage for analog operations ( ground ) Reference voltage for input signals Input op-amp single ended input signal for CAS, FSK and PTE Input op-amp positive input signal for CAS, FSK and PTE Input op-amp negative input signal for CAS, FSK and PTE Input op-amp output signal for CAS, FSK and PTE Input op-amp single ended input signal for DC Voltage level measurement Reference voltage for input signals Negative supply voltage for analog operations ( ground ) DTMF signal output Positive supply voltage for analog operations Positive supply voltage Resets the TCC110 to known state Interrupt output (active low) Bi-directional open drain pin for serial interface data input and output Test pin, must be floating Serial interface clock Positive supply voltage www.telechips.com Page 2 / 34 Tel: 82-2-3443-6792 www..com Specifications - June 2001 www.telechips.com D/A Converter DTM F G enerator Crystal O scillator XIN XO UT G ain Controller BandPass Filter FSK Receiver CAS Detector SDT SCK INT ADC Progress Tone Energy Detector BandPass Filter Ring Detector Frequency Counter M ode Control & Serial Interface ADC DC voltage m easurement Line Reversal / Ring Detector LRIN TEST TESTout RESET 2. BLOCK DIAGRAM DTM FO VREF1 VREF INS Figure 1. INP Page 3 / 34 INN Block diagram O UT IND VCCA VCCD VCCD Power Supply Circuit Tel: 82-2-3443-6792 VSSA VSSA VSSD VSSD TCC110 CIDCW receiver TCC110 www..com Specifications - June 2001 CIDCW receiver 3. APPLICATION DIAGRAM Tip/A Ring/B C2 R8 P1 R9 D6 R11 D5 R10 C1a C1b C4 C3 R6 C7 R13 R7 1 VSSD 2 LRin VCCD 24 SCK 23 R1a R1b Line IN R14 O ut R12 6 3 + 4 1 D1 D2 D3 D4 R15 3.579545MHz R18 C5 C6 3 TEST TESTOUT 22 4 Xin 5 Xout 6 VSSD 7 VSSA 8 VREF SDT 21 INT 20 RESET 19 VCCD 18 VCCA 17 DTMFO 16 VSSA 15 VREF1 14 IND 13 To micro controller 2 R2a R2b R16 C9 9 INS 10 INP 11 INN 12 OUT C8 DT M F_O UT R3 R4 R17 R5 TCC110 Figure 2. Recommended external components for typical application Table 2. Recommended external component values for typical application Differential input stage Single ended input stage C1a, C1b 2.2nF (1KV) C4 R1a, R1b 390K(0.5W) R6 R2a, R2b 47K R7 DC input stage R3 68K R4 220K R14,R15 R5 100K R16 D1, D2, D3, D4 IN4007 R17 Ring or Line Reversal Detector R18 C2 0.22uF (250V) C9 C3 10nF O1 Other components R8 36K R9 3.9K C5,C6 R10,R11 20K R12,R13 D5 24V C7,C8 D6 1N4148 X1 P1 PC817/LTV817 Notes on recommended external components : 100nF 100K 100K 10M 270K 330K 1K 1nF LM358 20pF 10K 10nF 3.579545MHz 0.1% Values for R6 and R7 are based on a hybrid that has a loss free path from LINE to OUT The components are specified for a typical application. For conformance to standards in certain applications, other component values and/or ratings may be necessary. www.telechips.com Page 4 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver 4. FUNCTION DESCRIPTION 4.1 Analog input and preprocessor The preprocessor for the FSK receiver and the CAS, the PTE detectors, comprises two input signal buffers, an Analog-to-Digital Converter (=ADC1) and digital bandpass filters. Bandpass filters are used to attenuate out band noise and interfering signals, which might otherwise reach the FSK receiver and CAS, PTE detectors. The CAS and PTE detectors share a single digital filter while the FSK receiver has its own separate filter. To measure the DC voltage of the telephone line, a DC input buffer and another Analog-to-Digital Converter (=ADC2) are used. The TCC110 can be forced into a power-down state by switching off the 3.579545 MHz system clock and all ADC's and op-amps. 4.1.1 Differential input buffer The differential input buffer is used to convert the balanced telephone line signal to the input signal of ADC1 in the TCC110. C1a Tip/A Ring/B C1b R1a INp INn + - to ADC1 R1b R2 C2a R4 R3 C2b OUT TCC110 VREF Figure 3. Differential input buffer of the TCC110 Design equations for this buffer are; The differential voltage gain = R4/R1b. R1a = R1b C1a = C1b R2 = R3 * R4 / (R3 + R4) The target differential voltage gain should be adjusted to obtain the expected signal level at the `OUT' pin. www.telechips.com Page 5 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 4.1.2 Single ended input buffer CIDCW receiver The single ended input buffer may also be used with the telephone line signal connected to the hybrid as shown in Figure 4. A C1c R5 INS Connected to Hybrid R6 C2c + - toADC1 TCC110 VREF Figure 4. Single ended buffer of the TCC110 The voltage gain is R6 / ( R5 + R6 ) The target voltage gain should be adjusted to obtain the expected signal level at the INS input. The BFS (Buffer selection) bit in the Function register chooses between the output of the single-ended input buffer and the output of the differential input buffer, sending the selected output to the ADC1. The differential input buffer is selected when BFS is `0' and the single ended input buffer is selected when BFS is `1'. The default value of BFS is `0' 4.1.3 DC input buffer The DC input buffer can be used to convert the telephone line voltage level to the ADC2 input voltage level. R14 Tip/A Ring/B R15 R17 6 3+ 2 4 1 IND R18 0 1 mux to ADC2 DCS R16 C9 VREF1 TCC110 Figure 5. DC input buffer of the TCC110 The range of telephone line voltages is determined by the register values at the input. The input range at IND can be from 0V to 5V. www.telechips.com Page 6 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 4.2 CAS tone detection CIDCW receiver The TCC110 CAS detection algorithm is capable of detecting the CAS signals during speech with high talk-down and talk-off performance without the use of a hybrid, and 100% Bellcore compliant performance with use of a hybrid. If the CAS detection is enabled the TCC110 will generate an interrupt (Interrupt register, bit 1 is set) when a correct dual tone (2130 and 2750 Hz) is detected. CAS detection is enabled when the CASenable bit in the Function register is set and the FSK and PTE enable bits in the Function register are cleared. The parameters of the CAS Detector are shown in table 1. Table 3: CAS detector parameters Parameter Low tone frequency High tone frequency Accepted signal level Twist Value 2130Hz 0.5% 2750Hz 0.5% -5.2dBm to -32dBm -6dB to +6dB When a valid CAS signal is detected, the CASdetect status bit of the Status register and the CASint bit of the interrupt register are set and an interrupt is generated. When the signal level is below the accepted signal level the status bit of the status register is cleared and the CASint interrupt bit is set , generating another interrupt. The CASint interrupt bit is reset when the interrupt register is read (see Figure 6). In order to accurately detect the end of a CAS tone, it is recommended to mute the near end speech immediately after the CAS tone has been detected. L in e s ig n a l C A S s ig n a l C A S d e te c t IN T Figure 6: CASdetect, CASint and INT related to the CAS tone 4.3 FSK reception 4.3.1 FSK data reception sequence The on-chip FSK Receiver satisfies all target specifications of Bellcore. The FSK receiver function can be enabled by setting the FSKenable bit (Function register, bit2) and clearing the CASenable (Function register, bit1) and the PTEenable (Function register, bit5) bits. When the FSK Receiver is enabled, the TCC110 continuously checks for a signal in the FSK band (~1200 ~2200 Hz) above the minimum signal level threshold. The TCC110 waits for mark bits, which are transmitted after www.telechips.com Page 7 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver the channel seizure. When mark bits are detected, the FSK receiver starts receiving FSK data bytes. An FSK data word consists of one start bit (space) followed by eight data bits and one stop bit (mark). After the FSK receiver has detected a start bit it starts receiving the data bits (LSB first). After the 8th data bit the FSKint interrupt bit (Interrupt register, bit2) is set and an interrupt is generated. The FSKint interrupt bit is cleared when the Interrupt register is read. The interrupt register and the FSKDT register should be read every time an interrupt occurs. F S K d a ta F S K in t IN T D0 D D1 D2 D3 D4 D5 D6 D7 D7 in te rr u p t r e g is te r is r e a d Figure 7. Sequence to receive an FSK data byte The parameters of the FSK receiver are shown in Table 4. Table 4: FSK Receiver parameters Parameter Mark frequency (logic 1) Space frequency (logic 0) Maximum allowed signal level Minimum signal level threshold Twist Accepted S/N (0Hz - 200Hz) Accepted S/N (200Hz - 3200Hz) Accepted S/N (3200Hz - 15000Hz) Transmission rate Bellcore 1200Hz 1% 2200Hz 1% 0dBm <-38dBm -10dB to +10dB <-20dB <6dB <-20dB 1200 bits per second 1% CCITT / V23 1300Hz 1.5% 2100Hz 1.5% -8dBV <-40dBV -6dB to +6dB <-20dB <6dB <-20dB 1200 bits per second 1% 4.3.2 Begin Of Mark (BOM) detection Due to noise etc. and the channel seizure signal the FSK receiver can mis-interpret the channel seizure or noise as normal data. This will cause the FSK receiver to generate unwanted interrupts before a BOM has been detected (see figure 9). The block of marks is a string of logic 1 and will not generate interrupts because there are no start bits. To prevent occurrence of unwanted interrupts, the BOMDC bit (Mode register, bit6) must be set to '0'. When this is done the BOMdetect bit (Interrupt register, bit6) will be set and the FSK interrupts will be generated after a mark period of at least 16 sequential 1's has been detected. Interrupt will therefore not be generated during the channel seizure and during the block of marks. The status of BOMdetect is available in the Interrupt register. BOMdetect itself does not generate an interrupt. This behavior is shown in Figure 8. This bit will be cleared when the FSK receiver is disabled or a signal drop out occurs for more than 18.3ms. In the latter case the FSK receiver will behave as if it has just been disabled. Page 8 / 34 www.telechips.com Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver The reset value of the BOMDC bit is `0' and this value is recommended to prevent unnecessary interrupt overloading of the micro-controller. F S K transm ission N oise Line signal C hannel seizure(optional) M ark D ata N oise F S K enabie B O M detect IN T lnterrpts due to noise and/or channel seizure lnterrpts due to noise on the line W hen B O M DC = 1 Figure 8: Interrupt behavior of the FSK receiver with BOMDC = 1 FSK transmission Noise Line signal Channel seizure(optional) Mark Data Noise FSK enabie BOMdetect INT lnterrpts due to noise on the line When BOMDC = 0 Figure 9: Interrupt behavior of the FSK receiver with BOMDC = 0 During FSK data reception, no new interrupts will occur after a signal dropout when BOMDC = '0'. If it is necessary to receive as much data as possible (even with a part missing) then the BOMDC can be set to '1' when reception of data starts. 4.4 Progress Tone Energy (PTE) detector This block is enabled when the TCC110 is set to PTE enable mode (Function register, bit5) and all the other functions in the Function register are disabled. The detector measures the total signal level for every 8.6ms. When the total signal level is above -27dBm in the Progress Tone band (305Hz to 640Hz ) the PTEdetect bit in the Status register is set. When the total signal level is below -27dBm the PTEdetect bit is cleared. Each time PTEdetect changes the PTEint bit is set and an interrupt is generated. The PTEint bit is cleared when the Interrupt register is read. This behavior is shown in Figure 10. www.telechips.com Page 9 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver L in e s ig n a l P T E s ig n a l P T E s ig n a l P T E d e te c t IN T ln t e r r u p t r e g is t e r is r e a d ln t e r r u p t r e g is t e r is r e a d ln t e r r u p t r e g is t e r is r e a d ln t e r r u p t r e g is t e r is r e a d Figure 10: PTE detector operation 4.4 DTMF generator The DTMF generator is able to generate 16 standard dual tones (see Table 5). These tones can be programmed by writing the DTMF register via the serial interface. The DTMF generator is enabled when the DTMFenable bit (Function register, bit3) is set to `1'. When the ONOFF bit in the DTMF register is programmed to '0', no tone will be generated; when it is programmed to '1', the tone specified in bits T3 to T0 will be generated. The code for each dual tone is shown in Table 5. The DTMFG register can control the output gain of DTMF signal. The default power of the DTMF signal is - 7.5dBm for high tone and -9.5dBm for low tone. The DTMFG register contains the gain factor that is multiplied to the default signal power to obtain the DTMF signal power. The gain factor is an unsigned number. The most significant bit (M) of the DTMFG register is the mantissa and the remaining bits (E6 to E0) denote the exponent. The output power of the DTMF signal can be obtained by the following equation. DTMF signal power = Default signal power * DTMFG Symbol DTMFG 7 M 6 E6 5 E5 4 E4 3 E3 2 E2 1 E1 0 E0 The DTMFG register can be programmed within the range from 0.0000001B (0.0078 in decimal) to 1.1000111B (1.5546 in decimal). For example, if DTMFG is set to 80H (1.0000000 in binary or 1.0 in decimal) the DTMF signal power will be the same as the default power. If the DTMFG register is 0.1100110H (0.7969 in decimal) the DTMF signal power will be 1.97dB lower than the default power as follows. 20log(default power*0.7969 - default power) = 20log0.7969 The high tone power = -9.47dB The low Tone power = -11.47dB = -1.97dB www.telechips.com Page 10 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver Table 5: DTMF frequencies code table D3 D2 D1 D0 Character 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 0 1 0 1 1 * 1 1 0 0 # 1 1 0 1 A 1 1 1 0 B 1 1 1 1 C 0 0 0 0 D Low frequency 697.0Hz 697.0Hz 697.0Hz 770.0Hz 770.0Hz 770.0Hz 852.0Hz 852.0Hz 852.0Hz 941.0Hz 941.0Hz 941.0Hz 697.0Hz 770.0Hz 852.0Hz 941.0Hz High frequency 1209Hz 1336Hz 1477Hz 1209Hz 1336Hz 1477Hz 1209Hz 1336Hz 1477Hz 1336Hz 1209Hz 1477Hz 1633Hz 1633Hz 1633Hz 1633Hz 4.5 Ring or line reversal detector For ring or line reversal detection, some external components are needed to generate a pulse each time a ring or line reversal occurs, as shown in Figure 11. Interrupt generation of the ring or line reversal detector is controlled by the LRenable bit in the Function register. When LRenable is set to `1', the LRint bit of the interrupt register will be set and interrupts will be generated at every transition of the LRstatus bit. When LRenable is `0', interrupts will not generated. The LRstatus bit ( reset value is high) in the Status register is cleared to `0' at any positive edge of the LRin. If no positive edges of LRin are detected in Tguard time the LRstatus bit is set to `1'. The LRint bit is cleared when the Interrupt register is read. C2 T ip /A R8 P1 R11 L R in D5 R10 C3 R in g /B to R in g / L in e re v e rs a l d e te c to r R9 D6 TCC120 Figure 11. External component to generate LRin If an LRint interrupt has been generated in power-down mode, it is recommended to disable power-down mode to www.telechips.com Page 11 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 be able to count the guard time counter using the main clock (XIN). CIDCW receiver The guard time counter is reset at the positive edge of LRin. The guard time (Tguard) can be programmed by writing the GTIME register as follows. Tguard = 143us * ( GTIME[6:0] * 4 + 3 ) (Ex. Tguard = 34.749ms = 0.143ms * (0111100B * 4 + 3 ) ) Figure 11 and Figure 12 show line reversal and ring detection respectively. Line signal LRin LRstatus PWD = 0 LRint INT PWD = 1 LRenable = 1 T guard Interrupt register is read Figure 12 : Behavior of signals on a line reversal Line signal LRin LRstatus LRint INT Tguard Interrupt register is read Interrupt register is read Figure 13: Behavior of signals during ring www.telechips.com Page 12 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 4.6 DC voltage measurement block DC voltage measurement block is shown in Figure 14. CIDCW receiver The DC voltage measurement block can measure the DC voltage on the telephone line to check multiple extension interoperability. Tip/A VC C IND 0 1 m ux AD C 2 D CS D C voltage m easurem ent block D1 D2 D3 D4 D 10 R 10a R 10c R 10b C 10 R ing/B VR E F1 TCC110 To serial Interfac e block Figure 14: DC voltage measurement block The voltage at IND is determined by: IND = (VTip - VRing) * ( (R10b+R10c) / (R10a+R10b+R10c) ) The reference voltage (VREF1) level can be measured by setting the reference voltage measurement mode. When the reference voltage measurement mode is set (DCM[1:0] = 01), the measured reference voltage level ( VREF1 ) is stored in the VREF1 data register (see Figure 19). But do not use this mode in application. The measured DC voltage on the telephone line is obtained as follows: DCdata =K * IND where K is 51 and DCdata is a signed 9 bit value. DCD0 and the LSB of DCD1 contain the data of DCdata and the sign bit, respectively. Each time a new value is stored in DCdata, its absolute value is compared with two programmable positive 8-bit thresholds (DCTH and DCTL). The comparison result is presented in the DC-HIGH and DC-LOW bits ( comparison status bits ) of the Status register. The meanings of these bits are shown in Table 6 and Figure 15. Table 6: Meanings of values in DC-HIGH and DC-LOW Bit DC-HIGH Value 1 0 1 DC-LOW 0 Meaning | DCdata | >= DCTH | DCdata | < DCTH | DCdata | >= DCTL | DCdata | < DCTL With these bits it is possible to detect easily whether the line voltage goes up or down by programming the thresholds such that DCTH is above the current DCdata value and DCTL is below the current DCdata value www.telechips.com Page 13 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver -D C T L -D C T H 0V DCTL DCTH D C d a ta D C -H IG H D C -L O W Figure 15: Behavior of DC-HIGH and DC-LOW related to DCdata, DCTH and DCTL 4.6.1 DC measurement time The time period for calculating the average value of the DC line voltage is programmed with the DC measurement time register (DCMT): Tmeasure = DCMT * 143us DCMT should be a power of 2. ( 2, 4, 8, 16, 32, 64, 128 ) 4.6.2 Interrupt generation by the DC voltage measurement block The way interrupts are generated is determined by the DC-INT mode bit in the Mode register. When DC-INT mode = 0, interrupts are generated when a change in the comparison status bits occurs (see Figure 16) When DC-INT mode = 1, interrupts are generated each time a new measurement has been completed (see Figure 17). Each time an interrupt is generated the DCint interrupt bit is set. The DCint interrupt bit is cleared when the Interrupt register is read. To prevent unpredictable behavior when programming new thresholds, be sure that the new threshold values are programmed before a new measurement time has expired. T m e a s u re L in e V o lta g e DCTH D C d a ta D C -H IG H D C -L O W D C in t IN T P ro g ra m n e w th re s h o ld s DCTL P ro g ra m n e w th re s h o ld s Figure 16: Interrupt generation of the DC voltage measurement block when DC-INT mode = 0 www.telechips.com Page 14 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver T m e a s u re L in e V o lta g e DCTH D C d a ta D C -H IG H D C -L O W D C in t IN T P ro g ra m n e w th re s h o ld s DCTL P ro g ra m n e w th re s h o ld s Figure 17: Interrupt generation of the DC voltage measurement block when DC-INT mode = 1 4.6.3 DC voltage measurement mode The DC voltage measurement block has four modes in which it can operate. These modes are selected with the DMC1 and DCM0 bits in the Mode register. The mode selection is shown in Table 6. Table 6: Description of the DC voltage measurement modes DCM1 DCM0 Mode Description DC line voltage measurement 0 0 DCdata = IND - VREF1 (DCS = 0) mode Reference voltage Reference voltage (VREF1) level is measured in this 0 1 measurement mode mode ( DCS = 1 ) - Do not use 1 1 Reserved 1 0 reserved 4.6.3.1 DC line voltage measurement mode VR E F1 data IN D 0 D C data mux 1 DCS AD C 2 DC m easuring DC data C om parison unit D C -H IG H D C -LO W D C TH D C TL VR E F1 TCC110 Figure 18: DC measurement block configuration for DC line voltage measurement mode www.telechips.com Page 15 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver In DC voltage measurement mode the data coming from the DC measuring unit is subtracted by the VREF1 data register. The result is passed to DCdata and the comparison unit (see Figure 18). In the comparison unit the absolute value of DCdata is compared with DCTH and DCTL. The result is presented in the DC-HIGH and DCLOW bits of the Status register. 4.6.3.2 Reference voltage measurement mode. ( Do not use this mode in application ) To obtain the reference voltage (VREF1) data the reference voltage measurement mode is used. In this mode the voltage at IND is ignored and the reference voltage (VREF1) is selected to determine the reference voltage level. The reference voltage measurement is done within the time specified in the DCMT register. The result of the measurement is written into the VREF1 data register (see Figure 19) When in this mode the status bits (coming from the Comparison unit) are not updated. The result of the reference voltage measurement can be used by the TCC110 in the DC voltage measurement mode. VREF1 d a ta IN D 0 D C d a ta m ux 1 DCS ADC2 DC m e a s u rin g DC d a ta C om p a riso n u n it D C -H IG H D C -L O W DCTH DCTL VREF1 TC C 110 Figure 19: DC Level Detector configuration for reference voltage measurement mode The VREF1 data register is an internal register that cannot be accessed via the serial interface. NOTE: Since reference voltage may change in time (due to change of temperature, supply voltage, etc.) it is recommended to measure the reference voltage regularly. 4.7 Ring detection signal from differential buffer signal from single ended buffer mux ADC1 RingD Ring Detector RingP FCint Frequency Counter FCNT To Serial Interface BFS RNGT TCC110 Figure 20: www.telechips.com Ring detection and frequency counting block Page 16 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver The TCC110 can extract the ring signal and its frequency (see Figure 20).. The ADC1 is used for converting the ring signal to the digital signal (RingD) and the ring detector removes the DC level of the RingD signal. The result is compared with the RNGT register. When the amplitude of RingD is higher than RNGT, pulses (RingP) are sent to the frequency counter. The frequency counter then generates interrupts (when enabled) and provides information about the ring frequency The minimum amplitude threshold of the ring signal that must be detected can be programmed via the RNGT register. The threshold is an 8-bit positive value. The higher the threshold is, the higher the ring amplitude must be in order to be detected. The behavior of RingP is shown in Figure 21. RNGT 48V 0V RNGT RingP FCint FCNT 255 fc1 fc2 fc3 fc4 fc5 fc6 fc7 fc8 fc9 fcA fcB fcC fcD 255 Figure 21: Behavior of RING when a ring occurs on the line (FCint only behaves as shown when FCenable = 1) 4.8 Frequency counter The frequency counter is enabled when the FCenable bit in the Function register is set. When the frequency counter is enabled, it counts the time between two positive edges of the RingP signal from the Ring Detection block. On every positive edge of RingP the current result is written into the FCNT register, the FCint bit is set and an interrupt is generated (see Figure 21, where fc1, fc2, ... , fcD and 255 are frequency counting results at each positive edge of the RingP signal ) When the frequency counter has reached its maximum value (255), it stops counting, writes 255 into the FCNT register, sets the FCint bit and generates an interrupt. When 255 is read from the FCNT register this means that the end of the ring has been reached. The FCint interrupt bit is cleared when the Interrupt register is read. FCNT represents the counted time as follows: T = FCNT * 0.572ms www.telechips.com Page 17 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 4.9 Serial Interface CIDCW receiver The serial interface is accessed through the SDT and SCK pins. The SDT pin is an open drain bi-directional pin (its output can be HiZ or logic0). 4.9.1 Serial bus configuration The serial bus consists of the SDT with a pull-up resistor (Rpu) and the SCK for each TCC110. The SCK is a transmission clock and the SDT transmits bi-directional data. The micro-controller always initiates a transmission and generates the transmission clock on the SCK line. When multiple TCC110s are used, all TCC110s are connected in parallel to the SDT line and each TCC110 has its own serial clock (SCK) from the micro-controller. Only the TCC110 of which the SCK is active is accessible and only one SCK may be active at any time. Vdd ( 5V ) Rpu SC K2 SC K1 M ic ro C o n tro lle r SD T SC K SDT TCC 110 SC K SDT TCC 110 Figure 22: Serial bus configuration 4.9.2 Start and stop conditions The SDT and SCK lines remain high when the bus is not busy. A high-to-low transition of the SDT line while the SCK is high is defined as the start condition. A low-to-high transition of the SDT while the SCK is high is defined as a stop condition When a start condition occurs between a normal start condition and a stop condition, this is called a repeated start condition. SCK SDT Start condition Stop condition Figure 23: Start and stop conditions www.telechips.com Page 18 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 4.9.3 Bit transfer CIDCW receiver After a start condition one data bit is transferred during each SCK pulse. The data on the SDT line must remain stable during the high period of the SCK pulse as changes in the data line at this time will be interpreted as a control signal SCK SDT d a t a lin e s t a b le ; d a t a v a lid c h a n g e o f d a ta a llo w e d Figure 24. Bit transfer timing 4.9.4 Byte transmission and acknowledge The number of data bytes transferred between the start and the stop conditions from the transmitter to the receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a high level signal put on the bus by the transmitter during which time the micro-controller generates an extra acknowledge-related clock pulse. The TCC110 must generate an acknowledge after the reception of address field data or a register start address. Also the micro-controller must generate an acknowledge after the reception of each byte that has been clocked out of the TCC110. The device that acknowledges must pull down the SDT line during the acknowledge clock period immediately after the 8 SCK pulse, so that the SDT line is stable low during the high period of the acknowledge-related SCK pulse. The micro-controller must signal an end-of-data to the TCC110 by not generating an acknowledge on the last byte that has been clocked out of the TCC110. In this event the TCC110 must leave the SDT line high to enable the micro-controller to generate a stop condition. th S C K fro m m ic ro c o n tro lle r S D T b y tra n s m itte r D7 D6 D5 D4 D3 D2 D1 D0 D7 ACK S D T b y re c e iv e r Figure 25. Byte transmission and acknowledge www.telechips.com Page 19 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 4.9.5 Address field CIDCW receiver Before any data is transmitted on the SDT line, the TCC110, which should respond, is addressed first. The addressing is always carried out with the first byte (Address field) transmitted after the start procedure. The interface address is reserved for the TCC110, 30H for write and 31H for read. When the address matches the address of the TCC110, the acknowledge is given; when it does not match, no acknowledge is given. The address field is built of two parts as follows - Interface Address (A6 to A0) - Read/Write control (R/W) A6 0 A5 0 A4 1 A3 1 A2 0 A1 0 A0 0 R/W 1/0 Figure 26: Specification of the bits of the address field 4.9.6 Register address The register address is the second byte transmitted by the micro-controller. This address is stored in the TCC110 and used for the following read and write actions. When multiple bytes are accessed, the first byte is written to the specified register address and the register address of the TCC110 is auto-incremented on each acknowledge. 4.9.7 Serial communication protocol The serial communication protocol is shown in Figure 27 and Figure 28. The micro-controller can initiate two kinds of sequence, the write sequence and the read sequence. Both sequences are initiated with a start condition that is followed by the TCC110 address with the read/write control bit cleared. The first byte after the TCC110 address is interpreted as the address of a TCC110 register. During the write sequence the register address of the TCC110 is increased automatically on each acknowledge. The write sequence is ended with the stop condition from the micro-controller. R/W a u to in c re m e n t re g is te r a d dre s s s ta rt A d d re s s F ie ld 0 A R e g is te r A dd re s s A D a ta A s to p a c k n o w le d em e n t fro m 1 1 0 a c k n o w le d em e n t fro m 1 1 0 a c k n o w le d em e n t fro m 1 1 0 Figure 27: Write sequence of the serial interface For the read sequence, after a register address of the TCC110, a repeated start condition is generated by the micro-controller which is followed by the TCC110 address with the read/write control bit set. The data is read from the previously-set register address. When the micro-controller responds with an acknowledge the address of the register is auto incremented and the TCC110 will put the data from the next register on the SDT line. When the www.telechips.com Page 20 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver micro-controller stops giving an acknowledge the TCC110 will stop transmitting data and the micro-controller will generate a stop condition. When the read sequence is initiated with a start condition that is followed by the TCC110 address with the read/write control bit set, the data is read from the last set register address. (See Figure 28) R /W R e p e a te d s ta rt A R e g is te r A d d re s s A s ta rt A d d re s s F ie ld R /W a u to in c re a m e n t re g is te r a d d re s s s ta rt A d d re s s F ie ld 0 1 A D a ta A a c k n o w le d g e m e n t fro m T C C 1 1 0 a c k n o w le d g e m e n t fro m T C C 1 1 0 a c k n o w le d g e m e n t fro m T C C 1 1 0 a c k n o w le d g e m e n t fro m m ic r o c o n tro lle r D a ta 1 s to p n o a c k n o w le d g e m e n t fro m m ic r o c o n tro lle r (a) R/W auto increament register address start Address Field 1A Data A Data 1 stop acknowledgement from TCC110 acknowledgement from micro controller no acknowledgement from micro controller (b) Figure 28: Read sequence of the serial interface (a) New register start address is programmed (b) No register start address is programmed. 4.10 Power-down mode The TCC110 can be put in power-down mode by programming the PDW bit in the Mode register to '1'. In this mode the input signal buffers, ADC's, the reference bias generator, the DTMF output buffer and the oscillator are switched off. However the Ring/Line Reversal detection can be active by programming the LRenable bit in the function register to be set. The serial interface can always be accessed, even in power-down mode. In powerdown mode, if ring or line reversal occur when LRenable bit is `1', the LRint bit is set and an interrupt is generated. When the TCC110 is put in power-down mode, all interrupt bits in the interrupt register cannot be set except for the LRint bit. 4.11 Interrupt The interrupt output (INT) is active low. The INT pin is in Hi-Z state when not active, so an external pull-up resister is required. The flag in the interrupt register indicates the interrupt cause. Interrupt flags are set by hardware but must be reset by software. All flags of the interrupt register are reset when the register is read via the serial interface. The Table 7 shows interrupt sources of the TCC110. www.telechips.com Page 21 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver Table 7: Interrupt sources of the TCC110 Source Block generation Ring / line reversal detector . When LRstatus changes Frequency counter . When a new measurement is started . When frequency counter reaches 255 FSK receiver . reception of a new FSK data byte DC voltage measurement . DC-INT mode = 0 : When DC-HIGH or DC-LOW changes block . DC-INT mode = 1 : Every time a new measurement has been completed CAS detector . When CASdetect changes PTE detector . When PTEdetect changes 4.12 3.579545MHz oscillator circuitry The on-chip oscillator is a single-stage-inverting amplifier biased by an internal feedback resistor. The oscillator circuit is shown in Figure 29. To drive the device with an external clock source, apply the external clock signal to XIN, and leave XOUT to float. If the amplitude of the input signal is less than VCC to VSS or a sign wave is applied, capacitive decoupling is needed. In the power-down mode (Mode register, bit7 = 1), the oscillator is stopped and XIN is internally pulled HIGH and the feedback path through the Rfd is opened to switch off the oscillator current. TCC110 lnternal circuit control TCC110 Rfd XIN XOUT XIN C9a C9b XOUT Sine wave Figure 29: (a) oscillator with external capacitor (b) External clock: sine wave www.telechips.com Page 22 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver 5. REGISTER MAPS The registers that are available in the TCC110 are shown in the following tables. Register overview Register name MODE FUNC DTMFT DCMT DCTH DCTL RNGT GTIME INTR STAT FSKDT FCNT DCD0 DCD1 DTMFG CONT1 CONT2 Address 00H 01H 02H 03H 04H 06H 08H 0aH 80H 81H 82H 83H 84H 85H f0H F1H F5H Function Mode register Function register DTMF tone select register DC measurement time register High DC threshold register Low DC threshold register Ring signal threshold register Guard time register Interrupt register Status register FSK data register Frequency counter register Measured DC data register Measured sign bit register of DC data DTMF output gain control register FSK control register 1 FSK control register2 Default value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Read / Write read / write read / write read / write read / write read / write read / write read / write read / write read only read only read only read only read only read only read / write read / write read / write Mode register (MODE) Address 00H; read / write. 7 PDW 6 BOMDC 5 4 3 DCenable 2 DC-INT mode 1 DCM1 0 DCM0 Description of MODE bits Bit MODE.7 MODE.6 MODE.3 MODE.2 MODE.1 & MODE.0 Symbol PWD BOMDC DCenable DC-INT mode DCM1 DCM0 Description 1: Puts the TCC110 in power-down mode 0: Puts the TCC110 in active mode 0: Forbids FSK interrupts until BOMDC is `1' 1: Allows FSK interrupts before BOMDC is `0' 1: Enables the DC Level measurement unit 0: Disables the DC Level measurement unit 1: The DC level measurement block generates an interrupt for every DC measurement time period. 0: The DC level measurement block generates an interrupt when DC-HIGH or DC-LOW status bit changes 00 : DC line voltage measurement mode 01 : Reference voltage measurement mode 10,11 : reserved www.telechips.com Page 23 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 Function register (FUNC) Address 01H; read / write. 7 BFS 6 5 PTEenable 4 FCenable 3 DTMFenable 2 FSKenable 1 CIDCW receiver 0 LRenable CASenable Description of FUNC bits Bit FUNC.7 FUNC.5 FUNC.4 FUNC.3 FUNC.2 FUNC.1 FUNC.0 Symbol BFS PTEenable FCenable DTMFenable FSKenable CASenable LRenable Description 1: Selects the single-ended input buffer 0: Selects the differential input buffer 1: Enables the PTE detector 0: Disables the PTE detector 1: Enables the frequency counter 0: Disables the frequency counter 1: Enables the DTMF generator 0: Disables the DTMF generator 1: Enables FSK receiver 0: Disables FSK receiver 1: Enables CAS detector 0: Disables CAS detector 1: Enables LR interrupts 0: Disables LR interrupts DTMF tone select register (DTMFT) Address 02H; read / write. 7 ON-OFF 6 5 4 3 T3 2 T2 1 T1 0 T0 Description of DTFMT bits Bit DTMFT.7 DTMFT.3 to DTMFT.0 Symbol ON-OFF T3 to T0 Description 1: Enables DTMF tone output 0: Disables DTMF tone output DTMF code to be generated (See table 999) DC measurement time register (DCMT) Address 03H; read / write. 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Description of DCMT bits Bit DCMT.7 to DCMT.0 Symbol D7 to D0 Description Determines the DC measurement period www.telechips.com Page 24 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 High DC threshold register (DCTH) Address 04H; read / write. 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 CIDCW receiver 0 D0 Description of DCTH bits Bit DCTH.7 to DCTH.0 Symbol D7 to D0 Description High threshold value to be compared with the measured DC voltage. Low DC threshold register (DCTL) Address 06H; read / write. 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Description of DCTL bits Bit DCTL.7 to DCTL.0 Symbol D7 to D0 Description Low threshold value to be compared with the measured DC voltage. Ring signal threshold register (RNGT) Address 08H; read / write. 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Description of RNGT bits Bit RNGT.7 to RNGT.0 Symbol D7 to D0 Description Threshold value to be compared with the absolute value of measured ring signal Guard time register (GTIME) Address 0aH; read / write. 7 6 G6 5 G5 4 G4 3 G3 2 G2 1 G1 0 G0 Description of GTIME bits Bit GTIME.6 to GTIME.0 Symbol D6 to D0 Description Guard time to indicate the end of a line reversal or ring Page 25 / 34 Tel: 82-2-3443-6792 www.telechips.com TCC110 www..com Specifications - June 2001 Interrupt register (INTR) Address 80H; read only. 7 6 BOMdetect 5 PTEint 4 FCint 3 DCint 2 FSKint 1 CIDCW receiver 0 LRint CASint Description of INTR bits Bit INTR.6 INTR.5 INTR.4 INTR.3 INTR.2 INTR.1 INTR.0 Symbol BOMdetect PTEint FCint DCint FSKint CASint LRint Description 1: Indicates that the Begin Of the Mark period during FSK reception has been detected 1: Indicates that PTEdetect has been changed 1: Indicates that a frequency counter result is stored and starts new counting. 1: Indicates that a DC interrupt has occurred (depends on DC-INT mode) 1: Indicates that a new FSK frame has been received 1: Indicates that CASdetect has been detected 1: Indicates that LRstatus has been changed Status register (STAT) Address 81H; read only. 7 6 5 PTEdetect 4 3 DC-HIGH 2 DC-LOW 1 CASdetect 0 LRstatus Description of STAT bits Bit STAT.5 STAT.3 STAT.2 STAT.1 STAT.0 Symbol PTEdetect DC-HIGH DC-LOW CASdetect LRstatus Description 1: Indicates that the PTE detector detects the signal that satisfies the specified frequency and energy level; 0: No more Progress Tone is detected 1: | measured DC voltage | >= DCTH ( When DCenable is `1' ) 0: | measured DC voltage | < DCTH ( reset value ) 1: | measured DC voltage | >= DCTL ( reset value ) 0: | measured DC voltage | < DCTL ( When DCenable is `1' ) 1: Indicates that a CAS tone has been detected 0: No more CAS Tone is detected 1: LRint has not occurred until expiring GTIME (reset value) 0: LRint has occurred before expiring GTIME FSK data register (FSKDT) Address 82H; read only. 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 www.telechips.com Page 26 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 Description of FSKDT bits Bit FSKDT.7 to FSKDT.0 Symbol D7 to D0 Description Last received FSK data byte CIDCW receiver Frequency counter register (FCNT) Address 83H; read only. 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Description of FCNT bits Bit FCNT.7 to FCNT.0 Symbol D7 to D0 Description Last measured frequency data Measured DC data register (DCD0) Address 84H; read only. 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Description of DCD0 bits Bit DCD0.7 to DCD0.0 Symbol D7 to D0 Description Last measured DC voltage of the telephone line Measured DC data sign bit register (DCD1) Address 85H; read only. 7 6 5 4 3 2 1 0 SIGN Description of DCD1 bits Bit DCD0.0 Symbol SIGN Description Last measured sign bit of the DC voltage of the telephone line DTMF output gain control register (DTMFG) Address f0H; read / write 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 www.telechips.com Page 27 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 Description of DTMFG bits Bit DTMFG.7 to DTMFG.0 Symbol D7 to D0 Description CIDCW receiver This byte multiplied to control the output gain of DTMF generator Special control register (CONT1) Address f1H; read / write 7 6 5 4 3 0 2 1 1 1 0 1 This register should be written with `07h'. Special control register (CONT2) Address f5H; read / write 7 6 5 0 4 0 3 0 2 0 1 0 0 0 This register should be written with `00h'. Notes: 1. To allow for future extensions, reserved bits (indicated with `-`) must be written with '0'. 2. When reading from a register, the reserved bits (indicated with `-`) return an undefined value (either '0' or '1'). 3. The value of DCMT register should be power of 2 ( 0, 2, 4, 8, 16, 32, 64, 128 ) www.telechips.com Page 28 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver 6. 6.1 ELECTRICAL SPECIFICATIONS Absolute maximum ratings Parameter DC supply voltage ( VCCA, VCCD ) DC input voltage DC input current Storage temperature Min -0.3 -0.3 -10 -40 Max 7 VCC+0.3 10 125 Unit V V mA C Symbol VCC VIN IIN Tstg 6.2 DC electrical characteristics Parameter DC supply voltage ( VCCA, VCCD ) Min 4,75 Typ 5.0 Max 5.25 Unit V VDD = 5V 5%, TA = 0 to 70C, XIN = 3.579545MHz 0.1% Symbol VCC Logical inputs and outputs (pins SCK, SDT, INT, RESET, LRin, TEST, TESTOUT) VIH VIL VT+ VTIIH IIL VOH VOL High level input voltage Low level input voltage Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current (VIN = VCC) Low level input current (VIN = VSS) Low level input current with pull-up High level output voltage ( IOH=4mA ) Low level output voltage ( IOL=4mA ) 0.2VCC -10 -10 -100 2.4 0.4 -50 10 10 -10 0.7VCC 0.3VCC 0.8VCC V V V V uA uA uA V V 6.3 Electrical characteristics Parameter Min Typ Max Unit VDD = 5V 5%, TA = 0 to 70C, XIN = 3.579545MHz 0.1% Symbol Crystal Oscillator Fx Tol Cxi,Cxo Normal frequency Frequency tolerance Input capacitance on XIN and XOUT -0.1 7 3.579545 0.1 MHz % pF Voltage reference VREF Reference voltage output 2.25 V CAS detector THac Pic Input accept threshold (in 600 load ) Input signal power ( in 600 load ) -32 -32 0 dBm dBm www.telechips.com Page 29 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 VDD = 5V 5%, TA = 0 to 70C, XIN = 3.579545MHz 0.1% Symbol flc fhc fmaxc Twc Parameter Low tone frequency High tone frequency maximum frequency deviation Twist -0.6 -6 Min Typ 2130 2750 +0.6 6 Max CIDCW receiver Unit Hz Hz % dB FSK receiver Pif fD fmb fsb fmv fsv Twf S/N0 S/N1 S/N3 Input signal power ( in 600 load ) data transmission rate frequency mark frequency (Bell202) space frequency (Bell202) mark frequency (CCITT/V23) space frequency (CCITT/V23) twist signal to noise ratio (0Hz - 200Hz) signal to noise ratio (200Hz - 3.2kHz) signal to noise ratio (3.2kHz - 15kHz) -10 -25 6 -25 -38 1188 1188 2178 1200 1200 2200 1300 2100 10 0 1212 1212 2222 dBm Baud Hz Hz Hz Hz dB dB dB dB Progress tone energy detector BW THap detection bandwidth Input accept threshold (in 600 load ) 305 -27 640 0 Hz dBm Analog Input of A/D converter Vadc1 Vadc2 Aimp voltage range of ADC1( OUT pin ) voltage range of ADC2 ( INSE pin ) Analog input impedance 10 2.828 2.1739 Vp-p Vp-p k www.telechips.com Page 30 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 6.4 AC Timing values CIDCW receiver CAS timing characteristics Parameter TDETC TOFFC TWIDTHC Min Typ 51.6 25.8 Max Unit ms ms ms 25.8 Line signal CAS signal CASdat INT TO FFC T DETC TW IDTHC Figure 30: Timing of the CAS detection signals related to the CAS tone PTE timing characteristics Parameter TDETP TOFFP Min Typ 18.3 18.3 Max Unit ms ms Line signal PTE signal PTEdetect INT T DETP T O FFP Figure 31: Timing of the PTE detection signals related to the progress tone www.telechips.com Page 31 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver Serial Interface timing characteristics Parameter Tstart Tstop TSCKL TSCKH Tsu (setup) Thd (hold) Min 50 50 500 500 50 50 Typ Max Unit ns ns ns ns ns ns SCK SDT T s ta rt T s to p S ta r t c o n d itio n S to p c o n d itio n Figure 32: Timing constraints of start and stop conditions SCK SDT Tsu Thd TSCKH TSCKL Figure 33: Timing of SCK and SDT during byte transmission www.telechips.com Page 32 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 CIDCW receiver 7. PACKAGE Package dimensions VSSD L R in TEST X IN XO UT VSSD VSSA VREF IN S IN P IN N OUT 1 2 3 24 23 22 VCCD SCK TESTO UT SDT IN T RESET VCCD VCCA DTM FO VSSA E B H L TCC110 TCC110 TCC110 4 5 6 7 8 9 10 11 12 21 20 19 18 17 16 15 14 13 A C F D G VR EF1 IN D Figure 34: 24-pin SOP package dimensions mm min A B C D E F G H L 15.2 0.33 1.27 2.35 0.1 7.4 10.00 0.23 0.4 0 max. 15.6 0.51 1.27 2.65 0.3 7.6 10.65 0.32 1.27 8 www.telechips.com Page 33 / 34 Tel: 82-2-3443-6792 TCC110 www..com Specifications - June 2001 Revision history May 25, 2001 LRin application circuit modified ( page 11 - figure 11 ) DC measurement mode (DCS) modified ( page 15 - table 6 ) DC_INT mode figure modified ( page 14 - figure 16. & page 15 - figure 17 ) Jun 8, 2001 TESTOUT(#22) pin should be not connected (floating). DC input buffer circuit is modified. ( page 6 - figure 5 ) CIDCW receiver www.telechips.com Page 34 / 34 Tel: 82-2-3443-6792 |
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